1/7 rev. b structure silicon monolithic integrated circuit product series lens control lsi type bu24026gu applications digital still cameras functions ?waveforming circuit (3 channels) ?pi driving circuit (2 cha nnels) ?driver block ( 1-6 channels) : constant voltag e control type h-bridge ?driver block (7 cha nnel) : constant current control type h-bridge absolute maximum ratings (ta ? 25 ? c) parameter symbol limits unit remark power supply voltage dvdd -0.34.5 v mvcc -0.37.0 v vddamp -0.37.0 v input voltage vin -0.3dvdd+0.3 v input/output current iin 500 driver block (by mvcc pin) 100 by piout pin storage temperature range tstg -55125 operating temperature range tope -2085 permissible dissipation pd 1.37 *1 this product is not designed fo r anti-radiation applications. *1to use at a temperature higher than ta=25, derate 13.7mw per 1. (at mounting 50 mm 58 mm 1.75mm glass epoxy board. ) operating conditions(ta ? 25 ? c) parameter symbol limits unit remark digital power supply voltage dvdd 2.73.6 dvddQmvcc driver power supply voltage mvcc 2.75.5 constant current control amplifier power supply voltage vddamp 2.75.5 clock operating frequency fclk 127.5 reference clock
2/7 rev. b electrical characteristics (unless otherwise specified, ta ? 25 ? c, dvdd ? 3.0v, mvcc ? 5.0v, vddamp ? 5.0v, dvss ? mgnd ? 0.0v) parameter symbol limits unit condition min. typ. min. quiescence (dvdd) issd - 30 100 ? cmd_rs=0 (mvcc) issvm - 0 5 ? cmd_rs=0 operation (dvdd) iddd - 8.5 15.0 cmd_rs=1 low-level input voltage vil dvss 0.3dvdd v high-level input voltage vih 0.7dvdd dvdd v low-level input current iil 0 10 ? vil = dvss high-level input current iih 0 10 ? vih = dvdd low-level output voltage vol dvss 0.2dvdd v iol = 1.0ma high-level output voltage voh 0.8dvdd dvdd v ioh = 1.0ma output voltage pivo - 0.28 0.50 v iih = 50ma detective voltage range v th 0.5 - 2. 5 v si1 detective voltage error v 1/2dvdd - 0.1 1/2dvdd 1/2dvdd + 0.1 waveforming vth = 20h setting high-level threshold voltage 1 1 . 9 v si2si3 (dvdd=3.25v), hys on low-level threshold voltage 1 0 . 6 v si2si3 (dvdd=3.25v), hys on hysteresis width 0.2 0.6 v si2si3 (dvdd=3.25v), hys on threshold voltage 2 1.0 1.85 v si2si3 (dvdd=3.25v), hys off on-resistance ron - 1.5 2.0 io = 100ma off-leak current ioz -10 0 10 ? output hiz setting turn-on time ton - 0.15 1.0 ? turn-off time toff - 0.1 0.5 ? average voltage accuracy vdiff -5 - +5 vdiff = 2.0v settin g . on-resistance ron - 0.9 1.5 io = 100ma off-leak current ioz -10 0 10 ? output hiz setting out p ut volta g e vo 188 200 212 mv dac setting: 1010_0111, rrnf=1[] turn-on time ton - 0.15 1.0 ? turn-off time toff - 0.1 0.5 ?
3/7 rev. b 3-wire serial interface control commands are framed by 16-bit serial input (msb first) and input through the csb, sclk, and sdata pins. 4 higher-order bits specify addresses, while the remaining 12 bits specify data. data of every bit is input through the sdata pin, retrieved on the rising edges of sclk. data becomes valid in the csb low area. the loading timing is different in the resistor. (as shown in note 5,6) furthermore, the interface w ill be synchronized with the falli ng edges of sclk to output the sout data of the 12 bits. address[3:0] data[11:0] 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 modea[1:0] sela[1:0] 0 ach different output voltage[6:0 ] 0 0 0 1 0 0 0 0 ach cycle[7:0] 0 0 1 0 ach cycle[15:8] 1 1 1 0 0 0 apos[1:0] 0 0 0 astop 0 0 1 0 ena rta ach pulse[9:0] 0 0 1 1 ach status[1:0] ach operation pulse number[9:0] 0 1 0 0 modeb[1:0] selb[1:0] 0 bch different output voltage [6: 0] 0 1 0 1 0 0 0 0 bch cycle[7:0] 0 0 1 0 bch cycle[15:8] 1 1 1 0 0 0 bpos[1:0] 0 0 0 bstop 0 1 1 0 enb rtb bch pulse[9:0] 0 1 1 1 bch status[1:0] bch operation pulse number[9:0] 1 0 0 0 modec[1:0] selc[1:0] 0 cch different output voltage [6: 0] 1 0 0 1 0 0 0 0 cch cycle[7:0] 0 0 1 0 cch cycle[15:8] 1 0 1 5_pwm_ct[1:0] 5ch different output voltage[6:0] 1 1 0 6_pwm_ct[1:0] 6ch different output voltage[6:0] 1 1 1 0 0 0 cpos[1:0] 0 0 0 cstop 1 0 1 0 enc rtc cch pulse[9:0] 1 0 1 1 cch status[1:0] cch operation pulse number[9:0] 1 1 0 0 0 0 chopping[1:0] cachem sel56[2:0] p_ctrl clk_div[2:0] 1 1 0 1 0 0 0 0 0 0 0 0 0 0 pi_ctrl1 pi_ctrl2 0 0 1 0 0 5_pulse_cnt 5_pulse_base[1:0] 0 6_pulse_cnt 6_pulse_base[1:0] 0 1 0 0 5_pulse_count[7:0] 0 1 0 1 6_pulse_count[7:0] 0 1 1 0 0 ext_en 0 ext_rt ext_num[3:0] 1 0 0 0 ext_pat1 ext_pat0 1 0 0 1 ext_pat3 ext_pat2 1 0 1 0 ext_pat5 ext_pat4 1 0 1 1 ext_pat7 ext_pat6 1 1 0 0 ext_pat9 ext_pat8 1 1 0 1 ext_pat11 ext_pat10 1 1 1 0 ext_pat13 ext_pat12 1 1 1 1 ext_pat15 ext_pat14 1 1 1 0 0 0 0 0 constant current driver reference voltage adjustment 8b it dac[7:0] 0 1 0 0 0 0 0 0 0 0 7_ctrl[1:0] 1 0 0 0 0 0 wavefoming circuit 1 vthh[5:0] 1 0 0 1 0 0 wavefoming circuit 1 vthl[5:0] 1 0 1 0 0 0 0 0 0 0 hys3 hys2 1 1 0 0 0 0 0 0 0 0 0 cmd_rs addresses other than those above setting prohibited (note 1) the notations a, b, c in the register map correspond to ach, bch and cch respectively. (note 2) the ach is defined as 1ch and 2ch driver output, the bch as 3ch and 4ch driver output, and cch as 5ch and 6ch drive r output. (note 3) after resetting (power on reset, and cmd_rs), initial setting is saved in all registers. csb d13 d14 d9 d8 d10 d11 d5 d4 d6 d7 d1 d0 d2 d3 x d15 x d12 address data scl k sdata d9 d8 d10 d11 d5 d4 d6 d7 d1 d0 d2 d3 x sout hiz hiz
4/7 rev. b (note 4) the addresses 4b0011, 4b0111, and 4b1011 have dat a (status[1:0] ,operation pulse number[9:0]), which are interna l register values and output from the sout pin. (note 5) for mode, different output voltage, cycle, en, and r t registers, data that are written before the access to the pul se register becomes valid, and determined at the rising edge of csb after the ac cess to the pulse register. (the mode, different output voltage, cycle, en, rt, and pulse registers contain ca che registers, but any registers other than those do not contai n with such registers.) (note 6) for pos, st op, pwm_ct, and different output voltage registers, data are determined at the rising edge of csb, and for any registers other than those, data are dete rmined at the rising edge of 16th sclk . block diagram in7 out3a mgnd34 mvcc34 out3b out4a mgnd34 mvcc34 out4b out5b mgnd56 mvcc56 out5a mvcc56 mgnd7 out7a thermal shut-down dvdd sense rnf + - vddamp fclk state3 in56 sout sdata sclk state2 cs state1 dvdd dvss so3 si3 so2 si2 so1 si1 piout1 out1a mgnd12 mvcc12 out1b out2a mgnd12 mvcc12 out2b piout2 dac dvdd dvdd dvdd out3a mgnd34 mvcc34 out3b out4a mgnd34 mvcc34 out4b out5b mgnd56 mvcc56 out5a out6b mgnd56 mvcc56 out6a out7b mgnd7 thermal shut-down dvdd logic sense rnf + - vddamp fclk state3 sout sdata sclk state2 csb state1 dvdd dvss so3 si3 so2 si2 so1 si1 piout1 out1a mgnd12 mvcc12 out1b out2a mgnd12 mvcc12 out2b piout2 dac dvdd dvdd dvdd low voltage detect dvdd power on reset dvdd analog feed-back pre- driver analog feed-back pre- driver analog feed-back pre- driver analog feed-back pre- driver analog feed-back pre- driver analog feed-back pre- driver
5/7 rev. b pin functions land pin name powe r function i/o handlin g of unused p ins e6 dvdd - di g ital p ower su pp l y power su pp l y - e2 dvss - ground gnd - c2 fclk dvdd main clock lo g ic in p ut i p ull down(dvss) d4 csb dvdd serial control chi p select in p ut i p ull u p (dvdd) b3 sclk dvdd serial control clock in p ut i p ull down(dvss) d3 sdata dvdd serial control data input i p ull down(dvss) b5 sout dvdd serial control data out p ut o o p en e4 state1 dvdd state1 1,2ch condition lo g ic out p ut o o p en f4 state2 dvdd state2 3,4ch condition lo g ic out p ut o o p en f5 state3 dvdd state 3 5,6ch condition lo g ic out p ut / 5,6ch control lo g ic in p ut io(initial conditiono) o p en d5 in56 dvdd 5,6ch control lo g ic in p ut i p ull down(dvss) c5 in7 dvdd 7ch control lo g ic in p ut i p ull down(dvss) e3 piout1 dvdd pi drivin g out p ut1 o o p en d2 piout2 dvdd pi driving output2 o o p en e5 si1 dvdd 1ch waveformin g in p ut(with ad j ustment function of threshold volta g e) i p ull down(dvss) b4 si2 dvdd 2ch waveformin g in p ut i p ull down(dvss) c6 si3 dvdd 3ch waveformin g in p ut i p ull down(dvss) f3 so1 dvdd 1ch waveformin g out p ut o o p en c4 so2 dvdd 2ch waveformin g out p u t o o p en d6 so3 dvdd 3ch waveformin g out p ut o o p en a1, b2 mvcc12 - 1-2channel driver power supply power su pp l y - a4 mgnd12 - 1-2channel driver ground gnd - a2 out1a mvcc12 1-channel driver a output o o p en a3 out1b mvcc12 1-channel driver b output o o p en a5 out2a mvcc12 2-channel drive r a out p ut o o p en a6 out2b mvcc12 2-channel driver b output o o p en a7, b6 mvcc34 - 3-4channel driver power supply power su pp l y - d7 mgnd34 - 3-4channel driver ground gnd - b7 out3a mvcc34 3-channel driver a output o o p en c7 out3b mvcc34 3-channel driver b output o o p en e7 out4a mvcc34 4-channel driver a output o o p en f7 out4b mvcc34 4-channel driver b output o o p en g5 mvcc56 - 5-6channel driver power supply power su pp l y - g3 mgnd56 - 5-6channel driver ground gnd - g6 out5a mvcc56 5-channel driver a output o o p en f6, g7 out5b mvcc56 5-channel driver b output o o p en g4 out6a mvcc56 6-channel driver a output o o p en g2 out6b mvcc56 6-channel driver b output o o p en d1 rnf - 7-channel driver power supply power su pp l y - b1 mgnd7 - 7-channel driver ground gnd - f2, g1 vddamp - power su pp l y of constant current drive r control power su pp l y - f1 sense vddamp ne g ative in p ut for constant current driver control i p ull down(mgnd7) e1 out7a rnf 7-channel drive r a out p ut o o p en c1 out7b rnf 7-channel drive r b out p ut o o p en c3 index - index p in - - it is not possible to use corner pin only. (corner pins are a1 , a7, g1, an d g7.) please use a1-b2, a7-b6, f2-g1, f6-g7 pair respectively or us ing b2, b6, f2, f6 only.
6/7 rev. b pin related equivalent circuit diagrams pin equivalent circuit diagram pin equivalent circuit diagram fclk, csb, sclk sdata, in56, in7, si2, si3 *si2,si3 are the schmitt inputs. sense sout, state1, state2, so1, so2, so3 piout1, piout2 out1a, out1b, out2a, out2b out3a, out3b, out4a, out4b out5a, out5b out6a, out6b out7a, out7b rnf state3 si1 dvdd dvss p vcc56 mgnd56 p p mgnd12 p p vcc12 mgnd34 p p vcc34 mgnd7 p p p rnf vddamp mgnd7 + - vddamp mgnd7 p dvdd dvss dvdd dvss p dvdd dvss dvdd dvss dvdd dvss p dvdd dvss dvdd dvss p dvdd dvss p
7/7 rev. b pin assignment diagram (reverse side) outline dimensions/marking figure ? vddamp outb mgnd outa mvcc outa outb sense vddamp so state state outb outb outa dvss piout state si dvdd outa rnf piout2 sdata csb in so mgnd out7b fclk so in si outb mgnd mvcc12 sclk si sout mvcc outa mvcc12 out1a out1b mgnd out2a outb mvcc 67 2345 c b a 1 g f e d vcsp85h3 cautions on use (1) absolute maximum ratings if applied voltage, operating temperature range, or other absol ute maximum ratings are exceeded, the lsi may be damaged. do no t apply voltages or temperatures that exceed the absolute maximum ratings. if you expect that any voltage or temperature could be exceeding the a bsolute maximum ratings, take physical safety measures such as fuses to prevent any conditions exceeding the absolute maximum ratings from bei ng applied to the lsi. (2) gnd potential maintain the gnd pin at the minimum voltage even under any oper ating conditions. actually check to be sure that none of the pins have voltage lo wer than that of gnd pin, including transient phenomena. (3) thermal design with consideration given to the permissible dissipation under a ctual use conditions, perform thermal design so that adequate m argins will be provided. (4) short circuit between pins and malfunctions to mount the lsi on a board, pay utmost attention to the orient ation and displacement of the lsi. faulty mounting to apply a voltage to the lsi may cause damage to the lsi. furthermore, the lsi may also be dama ged if any foreign matters enter between pins, between pin and power supply, or between pin and gnd of the lsi. (5) operation in strong magnetic field make a thorough evaluation on use of the lsi in a strong magnet ic field. not doing so may malfunction the lsi. 24026 (unit : mm)
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